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ASIC Timing & Power Engineer

Remote, Canada · Computer/Software
We are looking for a physical backend engineer with experience in DC-Shell, Primetime, and Primepower.

Requirement & Responsibilities

    • 10+ years in in RTL design (Verilog/SystemVerilog)
    • Experience in Primetime, Primepower, DC-shell, DC compiler, STA, Timing Closure (including Timing Closure using Primetime), CDC analysis, VCS, Low power design
    • Experience with Dynamic power analysis and design using VCD files and DC-shell/Power compiler/Primepower
    • Experience with Linux, Make, and Bash
    • Experience with Tcl
    • Good verbal and written communication skills
    • Ability to work independently and as part of a team
    • Problem-solving and trouble-shooting skills; ability to take initiative and solve problems
    • High performance IP RTL design with low power design techniques .
    • Focus on timing (writing constraints), STA, LINT and CDC closure to ensure high quality RTL, power analysis
    • Writing testbenches, simulation
    • title change to "ASIC Timing and Power Engineer"
    • in the preferred section, add:
    • knowledge of UPF flow for defining power intent of chips with multiple power domains
    • Lower experience from 10+ years to 7+ years

Preferred Skills & Experience

    • Good understanding PCI Express and Computer Architecture.
    • Knowledge of memory interfaces (DDR/LPDDR/etc.)
    • Working experience in Python/C/C++/Assembly
    • Working experience in verification with UVM.
    • Able to cross check between Primetime and Spice simulations
    • Team Lead experience
    • Experience with Spyglass (LINT, CDC)
    • Experience with Verilog Coding

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