Senior ASIC Digital Design Verification Engineer

We are looking for a RTL and gatelevel verification engineer with experience in UVM, VCS, Python.

Requirements & Responsibilities

•  
  • 10+ years in in RTL design (Verilog/SystemVerilog)
  • Experience in UVM, VCS, Python, Low power design
  • Writing test benches, simulation
  • High performance IP RTL design with low power design techniques
  • Good understanding of PCI Express
  • Good verbal and written communication skills
  • Ability to work independently and as part of a team
  • Problem-solving and trouble-shooting skills; ability to take initiative and solve problems

Preferred Skills & Experience

• • Good understanding of computer architecture
  • Knowledge of memory interfaces (DDR/LPDDR/etc.)
  • Working knowledge of Linux
  • Working experience in Python/C/C++/Assembly
  • Working experience in verification with UVM.
  • Team Lead experience
  • Experience with Spyglass (LINT, CDC)
  • Experience with Verilog Coding