Responsibilities:
Bring deep knowledge and experience in SOC design methodologies, share and imbed proper design methods into IP teams
Own SOC design; take responsibility for enabling team to build chip and tape it out
Create I/O ring to provide the necessary reliability protection across the entire SOC, and integrates I/O ring rules for different IPs
Design to prevent clocking failures
Assist in emulation, FPGA, prototyping efforts, silicon bring-up, debug and characterization
Work in collaboration with Packaging, PCB, and IP teams
Qualifications
Post-secondary education in electrical engineering, computer science, or a related field
Prior experience as an SOC designer on any chip (CPU, GPU, etc.)
Knowledge and experience with automation of full-chip integration, clocks, resets, interfaces, pad ring, I/Os
Possesses strong opinions on proper SOC design methods and ability to influence to develop standards and push them into IP teams
Proficiency in C++
Self-starter with excellent communication skills