Are you interested in joining a team that creates innovative hardware and delivers industry leading AI performance and efficiency? We ar looking for ASIC/FPGA Prototyping Design Engineers who own and drive the entire FPGA prototyping flow for the next generation AI accelerator.  This is a role for a versatile engineer that includes RTL design, verification, FPGA partitioning and implementation, and lab based bringup of the SoC, This position requires a wide range of skills, and exceptional problem solving ability. You will be working with architects, designers, software engineers, and verification teams to accomplish your tasks.

Responsibilities & Requeirements

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  • BS/MS/PHD in EE/CE/CS, or equivalent
  • 5+ years of experience in FPGA design, timing constraint and timing closure, analyzing and improving RTL hardware performance and area as well as lab bringup of FPGA
  • Good understanding of PCI Express 
  • Knowledge of memory interfaces (DDR/LPDDR/etc.)
  • Good verbal and written communication skills
  • Ability to work independently and as part of a team
  • Problem-solving and trouble-shooting skills; ability to take initiative and solve problems

Preferred Skills & Experience

• • Good understanding of computer architecture
  • Knowledge of RISC-V cores
  • Experience with conversion of ASIC design to FPGA for emulation or prototyping purpose
  • Experience with emulation or prototyping platform: Synopsys ZeBu/HAPS, Cadence Palladium/Protium or other platforms, including compilation, debug, performance and throughput tuning
  • Experience with various verification tasks - test plan development, test bench development, simulation/waveform debug, coverage analysis
  • Working knowledge of Linux
  • Working knowledge of Python/Perl
  • Working experience in verification with SV/UVM.
  • Knowledge of Deep Learning concepts and frameworks is a plus