This candidate will contribute to a team developing IP for both FPGAs and ASICs. Our ideal candidate is a strong communicator, creative, a critical thinker, and able to analyze and resolve complex issues.
Responsibilities
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- Design, propose and oversee the analysis/evaluation of hardware architectures
- Design and code RTL modules written in Verilog/SystemVerilog
- Simulate and perform hardware-based testing, debug, and verification
- Scripting and basic software development in support of hardware design
- Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment
Requirements
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- B.S, M.S, or Ph.D in Electrical Engineering, Computer Engineering or Computer Science
- 5+ years of experience hardware systems design, experience analyzing and improving RTL hardware performance and area as well as lab bringup
- FPGA/ASIC development environment tools expertise, including design, implementation and debug
- Strong knowledge with RTL programming languages Verilog/SystemVerilog (preferred), or VHDL
- Ability to read and write code in Python (C, C++ are assets)
Preferred Skills & Experience
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- Deep experience with ASIC and FPGA programming including timing closure, resource management, and using IP libraries highly preferred
- Experience with Agile development methodologies
- Experience in technical leadership of small teams