This position is for a Formal Design Verification Engineer. The successful candidate will use formal verification technologies to perform functional verification of design blocks inside Custom Al IPs. Formal technologies include Formal Property Verification, Sequential Equivalence Checking and Data path Validation.

Responsibilities

• • Drive Formal Verification Methodology on multiple components inside Custom AI Inference IP. This is not limited to creating and executing verification plan, debugging issues and coverage closure.
  • Evaluating various formal verification technologies and flows.

Preferred Skills & Experience

• • Knowledge of a property checking language such as SystemVerilog Assertion (SVA) and understanding of HDL languages such as SystemVerilog or Verilog.
  • Familiar with AMBA protocols such as AHB, APB and AXI.
  • Knowledge of Computer Architecture. Familiar with RISC-V ISA.
  • Able to use scripting languages such as Python.
  • Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
  • 3+ years' experience with hands-on design verification with 2+ years in formal verification.